In a source synchronous environment, a data source (“transmitter”) transmits data to a data sink (“receiver”) at least partially responsive to a clock signal provided from the receiver to the transmitter. Delays in communication between the transmitter and the receiver, which may include both external and internal delays, can lead to differences in phase between the clock signal and a source timing signal. The source timing signal, provided from the transmitter to the receiver, conventionally is provided in parallel with the data.
Even though the clock signal and the source timing signal may be predicated on having the same frequency within some tolerance, phase differences make it problematic for the receiver to transfer the data from the source timing signal domain to a clock domain of the receiver, which may be the domain of the clock signal. Obtaining data from the transmitter and transferring such data into an internal clock domain of the receiver is known as “data recapture” or just “recapture.” Data recapture is made more problematic when the source timing signal is a non-free running clocking signal, such as a strobe signal. Non-free running clock signals from transmitters may be found in a variety of integrated circuits, including, but not limited to, Double Data Rate (DDR) memories and other source synchronous devices. In conventional DDR memories, a strobe signal having a number of clock cycles is transmitted in parallel with the data.
Conventionally, for a source synchronous interface to transfer data from one clock domain to another, an asynchronous first-in, first-out buffer (“FIFO”) was used. Use of a FIFO was problematic with non-free running timing signals, such as a strobe signal, where data was first registered in an input/output block. Data registered in an input/output block and then again in a FIFO made pipelining difficult when using a non-free running clock. System level delay calculations have a delay variance making use problematic. With respect to delay variance for example, memory vendors conventionally specify timing uncertainty, such as in the form of a minimum and a maximum delay. This can lead to having to slow clock signal frequency to account for such uncertainty.
Accordingly, it would be desirable and useful to provide data recapture for a source synchronous interface that avoids one or more of the above-mentioned limitations.